FPGA, ASIC, Logic Design Engineer.
experience in FPGA, ASIC, Logic design in a large corporate networking environment.
- RTL coding of complex logic.
- Test bench simulation, chip-level logic debug.
- Timing closure.
- Lab testing.
- Design documentation.
- FPGA synthesis, place & route.
- Excellent record of successful design on schedule.
ABC Inc. Any Town, NY
Senior Hardware Engineer 2003 – 2008
- Designed and implemented a MC6833x based Control Unit for managing all operations.
- Designed and implemented a MC6833x based Data Acquisition System for dynamic estimation.
- Developed an IEEE 802.6 token bus LAN for management and retrieval of real-time performance parameters.
- Served as primary Systems Engineer accompanying installations at various locations.
XYZ Corp. Any Town, NY
Principal Hardware Engineer 1998 – 2003
- Test bench and test case development for host bus adapters. ASICs featured PCI Express (PCIE) x16 Gen1-x8 Gen 2 and IB x4 DDR and dual port QDR interfaces.
- Worked with designers to debug new PCIE x16 core, PCS model, and SERDES .
- Generated PCIE x16 requirements and test plan.
- Lead PCIE compliance testing effort.
- Updated test bench for functionality worked with designers to debug.
- Parsed IBTA specification for enhanced features and generated requirements and test plans.
BCD Inc. Any Town, NY
Senior RF Hardware Engineer 1995 – 1998
- Design of 802.11b-g-a-n radios for outdoor environments.
- Vendor evaluation and development of key components such as power amplifiers, filters and transceivers to support required performance and cost targets.
- Extensive use of Agilent Design System (ADS) for modeling of power amplifiers, bias circuits, couplers, detectors, RF system analysis, materials and packaging.
- Evaluation and selection of PCB materials and surface finishes to meet cost, supply and manufacturing objectives.
- Supported compliance testing of all products for FCC and ETSI requirements resulting in first pass certification.
- Performed statistical analysis of pre-production product builds to set production limits and establish initial yields >90% and long term yields > 95%
- Evaluation of Active Distributed Antenna Systems (DAS) for WiMAX and UMTS.
- Languages Tools: Veri log, Synplicity, Xilinx ISE, Debussy, Modelsim, Chip scope
- Equipment: Oscilloscope, Logic Analyzer
- : PCI bus, PCI Express, LPC, Utopia Bus, I2C, PL4, Ethernet, DMA engine, ALU, floating point arithmetic, policer, memory interface (SDRAM, DDR), DCM, PLL, multi-clock domain design, high speed timing closure
EDUCATION & PROFESSIONAL DEVELOPMENT
- BSEE, Johns Hopkins University
- Design for Performance – A1 Technical Institute New York
Design with the Vertex 5 Family – A1 Technical Institute New York